/*
 * Copyright 2023 , NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef _FSL_INPUTMUX_CONNECTIONS_
#define _FSL_INPUTMUX_CONNECTIONS_

/*******************************************************************************
 * Definitions
 ******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections"
#endif

#define INPUTMUX_GpioPortPinToPintsel(port, pin) ((pin) + (PINTSEL_PMUX_ID << PMUX_SHIFT))

/*!
 * @addtogroup inputmux_driver
 * @{
 */

/*!
 * @name Input multiplexing connections
 * @{
 */

/*! @brief Periphinmux IDs */
#define TIMER0CAPTSEL0            0x20U
#define TIMER0TRIGIN              0x30U
#define TIMER1CAPTSEL0            0x40U
#define TIMER1TRIGIN              0x50U
#define TIMER2CAPTSEL0            0x60U
#define TIMER2TRIGIN              0x70U
#define FREQMEAS_REF_REG          0x180U
#define FREQMEAS_TAR_REG          0x184U
#define CMP0_TRIG_REG             0x260U
#define ADC0_TRIG0_REG            0x280U
#define QDC0_TRIG_REG             0x360U
#define QDC0_HOME_REG             0x364U
#define QDC0_INDEX_REG            0x368U
#define QDC0_PHASEB_REG           0x36CU
#define QDC0_PHASEA_REG           0x370U
#define QDC0_ICAP1_REG            0x374U
#define FlexPWM0_SM0_EXTA0_REG    0x3A0U
#define FlexPWM0_SM0_EXTSYNC0_REG 0x3A4U
#define FlexPWM0_SM1_EXTA1_REG    0x3A8U
#define FlexPWM0_SM1_EXTSYNC1_REG 0x3ACU
#define FlexPWM0_SM2_EXTA2_REG    0x3B0U
#define FlexPWM0_SM2_EXTSYNC2_REG 0x3B4U
#define FlexPWM0_FAULT_REG        0x3C0U
#define FlexPWM0_FORCE_REG        0x3D0U
#define PWM0_EXT_CLK_REG          0x420U
#define AOI0_MUX_REG              0x440U
#define USBFS_TRIG_REG            0x480U
#define EXT_TRIG0_REG             0x4C0U
#define CMP1_TRIG_REG             0x4E0U
#define LPI2C0_TRIG_REG           0x5A0U
#define LPSPI0_TRIG_REG           0x5E0U
#define LPSPI1_TRIG_REG           0x600U
#define LPUART0_TRIG_REG          0x620U

#define PMUX_SHIFT 20U

typedef enum _inputmux_index_t
{
    kINPUTMUX_INDEX_CTIMER0CAPTSEL0    = 0U,
    kINPUTMUX_INDEX_CTIMER0CAPTSEL1    = 1U,
    kINPUTMUX_INDEX_CTIMER0CAPTSEL2    = 2U,
    kINPUTMUX_INDEX_CTIMER0CAPTSEL3    = 3U,
    kINPUTMUX_INDEX_CTIMER1CAPTSEL0    = 0U,
    kINPUTMUX_INDEX_CTIMER1CAPTSEL1    = 1U,
    kINPUTMUX_INDEX_CTIMER1CAPTSEL2    = 2U,
    kINPUTMUX_INDEX_CTIMER1CAPTSEL3    = 3U,
    kINPUTMUX_INDEX_CTIMER2CAPTSEL0    = 0U,
    kINPUTMUX_INDEX_CTIMER2CAPTSEL1    = 1U,
    kINPUTMUX_INDEX_CTIMER2CAPTSEL2    = 2U,
    kINPUTMUX_INDEX_CTIMER2CAPTSEL3    = 3U,
    kINPUTMUX_INDEX_ADC0_TRIGSEL0      = 0U,
    kINPUTMUX_INDEX_ADC0_TRIGSEL1      = 1U,
    kINPUTMUX_INDEX_ADC0_TRIGSEL2      = 2U,
    kINPUTMUX_INDEX_ADC0_TRIGSEL3      = 3U,
    kINPUTMUX_INDEX_QDC0_ICAPSEL0      = 0U,
    kINPUTMUX_INDEX_QDC0_ICAPSEL1      = 1U,
    kINPUTMUX_INDEX_QDC0_ICAPSEL2      = 2U,
    kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL0 = 0U,
    kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL1 = 1U,
    kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL2 = 2U,
    kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL3 = 3U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL0      = 0U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL1      = 1U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL2      = 2U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL3      = 3U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL4      = 4U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL5      = 5U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL6      = 6U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL7      = 7U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL8      = 8U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL9      = 9U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL10     = 10U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL11     = 11U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL12     = 12U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL13     = 13U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL14     = 14U,
    kINPUTMUX_INDEX_AOI0_TRIGSEL15     = 15U,
    kINPUTMUX_INDEX_EXT_TRIGSEL0       = 0U,
    kINPUTMUX_INDEX_EXT_TRIGSEL1       = 1U,
    kINPUTMUX_INDEX_EXT_TRIGSEL2       = 2U,
    kINPUTMUX_INDEX_EXT_TRIGSEL3       = 3U,
    kINPUTMUX_INDEX_EXT_TRIGSEL4       = 4U,
    kINPUTMUX_INDEX_EXT_TRIGSEL6       = 6U,
    kINPUTMUX_INDEX_EXT_TRIGSEL7       = 7U
} inputmux_index_t;

/*! @brief INPUTMUX connections type */
typedef enum _inputmux_connection_t
{
    /*!< TIMER0 CAPTSEL. */
    kINPUTMUX_CtimerInp0ToTimer0Captsel                 = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp1ToTimer0Captsel                 = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp2ToTimer0Captsel                 = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp3ToTimer0Captsel                 = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp4ToTimer0Captsel                 = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp5ToTimer0Captsel                 = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp6ToTimer0Captsel                 = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp7ToTimer0Captsel                 = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp8ToTimer0Captsel                 = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp9ToTimer0Captsel                 = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp12ToTimer0Captsel                = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp13ToTimer0Captsel                = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp14ToTimer0Captsel                = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp15ToTimer0Captsel                = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp16ToTimer0Captsel                = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp17ToTimer0Captsel                = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp18ToTimer0Captsel                = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp19ToTimer0Captsel                = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Usb0StartOfFrameToTimer0Captsel           = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToTimer0Captsel                   = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToTimer0Captsel                   = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToTimer0Captsel                   = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToTimer0Captsel                   = 25U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp0ToTimer0Captsel                 = 26U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp1ToTimer0Captsel                 = 27U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp2ToTimer0Captsel                 = 28U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp3ToTimer0Captsel                 = 29U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToTimer0Captsel                    = 30U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToTimer0Captsel                    = 31U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M1ToTimer0Captsel                  = 33U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToTimer0Captsel                  = 34U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToTimer0Captsel                  = 35U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M1ToTimer0Captsel                  = 36U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToTimer0Captsel                  = 37U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToTimer0Captsel                  = 38U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToTimer0Captsel               = 39U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToTimer0Captsel               = 40U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToTimer0Captsel               = 41U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToTimer0Captsel               = 42U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToTimer0Captsel              = 43U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer0Captsel            = 44U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer0Captsel            = 45U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer0Captsel            = 46U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer0Captsel    = 48U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer0Captsel     = 49U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpspi0EndOfFrameToTimer0Captsel           = 52U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpspi0ReceivedDataWordToTimer0Captsel     = 53U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpspi1EndOfFrameToTimer0Captsel           = 54U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpspi1ReceivedDataWordToTimer0Captsel     = 55U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart0ReceivedDataWordToTimer0Captsel    = 56U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart0TransmittedDataWordToTimer0Captsel = 57U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer0Captsel     = 58U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart1ReceivedDataWordToTimer0Captsel    = 59U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart1TransmittedDataWordToTimer0Captsel = 60U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer0Captsel     = 61U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart2ReceivedDataWordToTimer0Captsel    = 62U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart2TransmittedDataWordToTimer0Captsel = 63U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer0Captsel     = 64U + (TIMER0CAPTSEL0 << PMUX_SHIFT),

    /*!< Timer1 CAPTSEL. */
    kINPUTMUX_CtimerInp0ToTimer1Captsel                 = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp1ToTimer1Captsel                 = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp2ToTimer1Captsel                 = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp3ToTimer1Captsel                 = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp4ToTimer1Captsel                 = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp5ToTimer1Captsel                 = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp6ToTimer1Captsel                 = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp7ToTimer1Captsel                 = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp8ToTimer1Captsel                 = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp9ToTimer1Captsel                 = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp12ToTimer1Captsel                = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp13ToTimer1Captsel                = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp14ToTimer1Captsel                = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp15ToTimer1Captsel                = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp16ToTimer1Captsel                = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp17ToTimer1Captsel                = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp18ToTimer1Captsel                = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp19ToTimer1Captsel                = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Usb0StartOfFrameToTimer1Captsel           = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToTimer1Captsel                   = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToTimer1Captsel                   = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToTimer1Captsel                   = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToTimer1Captsel                   = 25U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp0ToTimer1Captsel                 = 26U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp1ToTimer1Captsel                 = 27U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp2ToTimer1Captsel                 = 28U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp3ToTimer1Captsel                 = 29U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToTimer1Captsel                    = 30U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToTimer1Captsel                    = 31U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M1ToTimer1Captsel                  = 33U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToTimer1Captsel                  = 34U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToTimer1Captsel                  = 35U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M1ToTimer1Captsel                  = 36U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToTimer1Captsel                  = 37U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToTimer1Captsel                  = 38U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToTimer1Captsel               = 39U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToTimer1Captsel               = 40U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToTimer1Captsel               = 41U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToTimer1Captsel               = 42U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToTimer1Captsel              = 43U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer1Captsel            = 44U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer1Captsel            = 45U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer1Captsel            = 46U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer1Captsel    = 48U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer1Captsel     = 49U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpspi0EndOfFrameToTimer1Captsel           = 52U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpspi0ReceivedDataWordToTimer1Captsel     = 53U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpspi1EndOfFrameToTimer1Captsel           = 54U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpspi1ReceivedDataWordToTimer1Captsel     = 55U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart0ReceivedDataWordToTimer1Captsel    = 56U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart0TransmittedDataWordToTimer1Captsel = 57U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer1Captsel     = 58U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart1ReceivedDataWordToTimer1Captsel    = 59U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart1TransmittedDataWordToTimer1Captsel = 60U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer1Captsel     = 61U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart2ReceivedDataWordToTimer1Captsel    = 62U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart2TransmittedDataWordToTimer1Captsel = 63U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer1Captsel     = 64U + (TIMER1CAPTSEL0 << PMUX_SHIFT),

    /*!< Timer2 CAPTSEL. */
    kINPUTMUX_CtimerInp0ToTimer2Captsel                 = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp1ToTimer2Captsel                 = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp2ToTimer2Captsel                 = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp3ToTimer2Captsel                 = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp4ToTimer2Captsel                 = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp5ToTimer2Captsel                 = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp6ToTimer2Captsel                 = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp7ToTimer2Captsel                 = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp8ToTimer2Captsel                 = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp9ToTimer2Captsel                 = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp12ToTimer2Captsel                = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp13ToTimer2Captsel                = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp14ToTimer2Captsel                = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp15ToTimer2Captsel                = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp16ToTimer2Captsel                = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp17ToTimer2Captsel                = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp18ToTimer2Captsel                = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_CtimerInp19ToTimer2Captsel                = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Usb0StartOfFrameToTimer2Captsel           = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToTimer2Captsel                   = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToTimer2Captsel                   = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToTimer2Captsel                   = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToTimer2Captsel                   = 25U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp0ToTimer2Captsel                 = 26U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp1ToTimer2Captsel                 = 27U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp2ToTimer2Captsel                 = 28U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp3ToTimer2Captsel                 = 29U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToTimer2Captsel                    = 30U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToTimer2Captsel                    = 31U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M1ToTimer2Captsel                  = 33U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToTimer2Captsel                  = 34U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToTimer2Captsel                  = 35U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M1ToTimer2Captsel                  = 36U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToTimer2Captsel                  = 37U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToTimer2Captsel                  = 38U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToTimer2Captsel               = 39U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToTimer2Captsel               = 40U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToTimer2Captsel               = 41U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToTimer2Captsel               = 42U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToTimer2Captsel              = 43U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer2Captsel            = 44U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer2Captsel            = 45U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer2Captsel            = 46U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer2Captsel    = 48U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer2Captsel     = 49U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpspi0EndOfFrameToTimer2Captsel           = 52U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpspi0ReceivedDataWordToTimer2Captsel     = 53U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpspi1EndOfFrameToTimer2Captsel           = 54U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpspi1ReceivedDataWordToTimer2Captsel     = 55U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart0ReceivedDataWordToTimer2Captsel    = 56U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart0TransmittedDataWordToTimer2Captsel = 57U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer2Captsel     = 58U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart1ReceivedDataWordToTimer2Captsel    = 59U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart1TransmittedDataWordToTimer2Captsel = 60U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer2Captsel     = 61U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart2ReceivedDataWordToTimer2Captsel    = 62U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart2TransmittedDataWordToTimer2Captsel = 63U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer2Captsel     = 64U + (TIMER2CAPTSEL0 << PMUX_SHIFT),

    /*!< TIMER0 Trigger. */
    kINPUTMUX_CtimerInp0ToTimer0Trigger                 = 1U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp1ToTimer0Trigger                 = 2U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp2ToTimer0Trigger                 = 3U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp3ToTimer0Trigger                 = 4U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp4ToTimer0Trigger                 = 5U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp5ToTimer0Trigger                 = 6U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp6ToTimer0Trigger                 = 7U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp7ToTimer0Trigger                 = 8U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp8ToTimer0Trigger                 = 9U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp9ToTimer0Trigger                 = 10U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp12ToTimer0Trigger                = 13U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp13ToTimer0Trigger                = 14U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp14ToTimer0Trigger                = 15U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp15ToTimer0Trigger                = 16U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp16ToTimer0Trigger                = 17U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp17ToTimer0Trigger                = 18U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp18ToTimer0Trigger                = 19U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp19ToTimer0Trigger                = 20U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Usb0StartOfFrameToTimer0Trigger           = 21U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToTimer0Trigger                   = 22U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToTimer0Trigger                   = 23U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToTimer0Trigger                   = 24U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToTimer0Trigger                   = 25U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp0ToTimer0Trigger                 = 26U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp1ToTimer0Trigger                 = 27U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp2ToTimer0Trigger                 = 28U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp3ToTimer0Trigger                 = 29U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToTimer0Trigger                    = 30U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToTimer0Trigger                    = 31U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M1ToTimer0Trigger                  = 33U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToTimer0Trigger                  = 34U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToTimer0Trigger                  = 35U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M1ToTimer0Trigger                  = 36U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToTimer0Trigger                  = 37U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToTimer0Trigger                  = 38U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToTimer0Trigger               = 39U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToTimer0Trigger               = 40U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToTimer0Trigger               = 41U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToTimer0Trigger               = 42U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToTimer0Trigger              = 43U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer0Trigger            = 44U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer0Trigger            = 45U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer0Trigger            = 46U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer0Trigger    = 48U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer0Trigger     = 49U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpspi0EndOfFrameToTimer0Trigger           = 52U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpspi0ReceivedDataWordToTimer0Trigger     = 53U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpspi1EndOfFrameToTimer0Trigger           = 54U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpspi1ReceivedDataWordToTimer0Trigger     = 55U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart0ReceivedDataWordToTimer0Trigger    = 56U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart0TransmittedDataWordToTimer0Trigger = 57U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer0Trigger     = 58U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart1ReceivedDataWordToTimer0Trigger    = 59U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart1TransmittedDataWordToTimer0Trigger = 60U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer0Trigger     = 61U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart2ReceivedDataWordToTimer0Trigger    = 62U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart2TransmittedDataWordToTimer0Trigger = 63U + (TIMER0TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer0Trigger     = 64U + (TIMER0TRIGIN << PMUX_SHIFT),

    /*!< Timer1 Trigger. */
    kINPUTMUX_CtimerInp0ToTimer1Trigger                 = 1U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp1ToTimer1Trigger                 = 2U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp2ToTimer1Trigger                 = 3U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp3ToTimer1Trigger                 = 4U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp4ToTimer1Trigger                 = 5U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp5ToTimer1Trigger                 = 6U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp6ToTimer1Trigger                 = 7U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp7ToTimer1Trigger                 = 8U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp8ToTimer1Trigger                 = 9U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp9ToTimer1Trigger                 = 10U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp12ToTimer1Trigger                = 13U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp13ToTimer1Trigger                = 14U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp14ToTimer1Trigger                = 15U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp15ToTimer1Trigger                = 16U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp16ToTimer1Trigger                = 17U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp17ToTimer1Trigger                = 18U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp18ToTimer1Trigger                = 19U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp19ToTimer1Trigger                = 20U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Usb0StartOfFrameToTimer1Trigger           = 21U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToTimer1Trigger                   = 22U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToTimer1Trigger                   = 23U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToTimer1Trigger                   = 24U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToTimer1Trigger                   = 25U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp0ToTimer1Trigger                 = 26U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp1ToTimer1Trigger                 = 27U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp2ToTimer1Trigger                 = 28U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp3ToTimer1Trigger                 = 29U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToTimer1Trigger                    = 30U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToTimer1Trigger                    = 31U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M1ToTimer1Trigger                  = 33U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToTimer1Trigger                  = 34U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToTimer1Trigger                  = 35U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M1ToTimer1Trigger                  = 36U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToTimer1Trigger                  = 37U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToTimer1Trigger                  = 38U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToTimer1Trigger               = 39U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToTimer1Trigger               = 40U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToTimer1Trigger               = 41U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToTimer1Trigger               = 42U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToTimer1Trigger              = 43U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer1Trigger            = 44U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer1Trigger            = 45U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer1Trigger            = 46U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer1Trigger    = 48U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer1Trigger     = 49U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpspi0EndOfFrameToTimer1Trigger           = 52U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpspi0ReceivedDataWordToTimer1Trigger     = 53U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpspi1EndOfFrameToTimer1Trigger           = 54U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpspi1ReceivedDataWordToTimer1Trigger     = 55U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart0ReceivedDataWordToTimer1Trigger    = 56U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart0TransmittedDataWordToTimer1Trigger = 57U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer1Trigger     = 58U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart1ReceivedDataWordToTimer1Trigger    = 59U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart1TransmittedDataWordToTimer1Trigger = 60U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer1Trigger     = 61U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart2ReceivedDataWordToTimer1Trigger    = 62U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart2TransmittedDataWordToTimer1Trigger = 63U + (TIMER1TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer1Trigger     = 64U + (TIMER1TRIGIN << PMUX_SHIFT),

    /*!< Timer2 Trigger. */
    kINPUTMUX_CtimerInp0ToTimer2Trigger                 = 1U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp1ToTimer2Trigger                 = 2U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp2ToTimer2Trigger                 = 3U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp3ToTimer2Trigger                 = 4U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp4ToTimer2Trigger                 = 5U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp5ToTimer2Trigger                 = 6U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp6ToTimer2Trigger                 = 7U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp7ToTimer2Trigger                 = 8U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp8ToTimer2Trigger                 = 9U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp9ToTimer2Trigger                 = 10U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp12ToTimer2Trigger                = 13U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp13ToTimer2Trigger                = 14U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp14ToTimer2Trigger                = 15U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp15ToTimer2Trigger                = 16U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp16ToTimer2Trigger                = 17U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp17ToTimer2Trigger                = 18U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp18ToTimer2Trigger                = 19U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_CtimerInp19ToTimer2Trigger                = 20U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Usb0StartOfFrameToTimer2Trigger           = 21U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToTimer2Trigger                   = 22U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToTimer2Trigger                   = 23U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToTimer2Trigger                   = 24U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToTimer2Trigger                   = 25U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp0ToTimer2Trigger                 = 26U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp1ToTimer2Trigger                 = 27U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp2ToTimer2Trigger                 = 28U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp3ToTimer2Trigger                 = 29U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToTimer2Trigger                    = 30U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToTimer2Trigger                    = 31U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M1ToTimer2Trigger                  = 33U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToTimer2Trigger                  = 34U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToTimer2Trigger                  = 35U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M1ToTimer2Trigger                  = 36U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToTimer2Trigger                  = 37U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToTimer2Trigger                  = 38U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToTimer2Trigger               = 39U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToTimer2Trigger               = 40U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToTimer2Trigger               = 41U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToTimer2Trigger               = 42U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToTimer2Trigger              = 43U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToTimer2Trigger            = 44U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToTimer2Trigger            = 45U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToTimer2Trigger            = 46U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer2Trigger    = 48U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer2Trigger     = 49U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpspi0EndOfFrameToTimer2Trigger           = 52U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpspi0ReceivedDataWordToTimer2Trigger     = 53U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpspi1EndOfFrameToTimer2Trigger           = 54U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpspi1ReceivedDataWordToTimer2Trigger     = 55U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart0ReceivedDataWordToTimer2Trigger    = 56U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart0TransmittedDataWordToTimer2Trigger = 57U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart0ReceiveLineIdleToTimer2Trigger     = 58U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart1ReceivedDataWordToTimer2Trigger    = 59U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart1TransmittedDataWordToTimer2Trigger = 60U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart1ReceiveLineIdleToTimer2Trigger     = 61U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart2ReceivedDataWordToTimer2Trigger    = 62U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart2TransmittedDataWordToTimer2Trigger = 63U + (TIMER2TRIGIN << PMUX_SHIFT),
    kINPUTMUX_Lpuart2ReceiveLineIdleToTimer2Trigger     = 64U + (TIMER2TRIGIN << PMUX_SHIFT),

    /*!< Selection for frequency measurement reference clock. */
    kINPUTMUX_ClkInToFreqmeasRef           = 1U + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_FroOsc12MToFreqmeasRef       = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_FroHfDivToFreqmeasRef        = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_Clk16K1ToFreqmeasRef         = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_SlowClkToFreqmeasRef         = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_FreqmeClkIn0ToFreqmeasRef    = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_FreqmeClkIn1ToFreqmeasRef    = 8u + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToFreqmeasRef        = 9u + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToFreqmeasRef        = 10u + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToFreqmeasRef = 11u + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig1ToFreqmeasRef = 12u + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToFreqmeasRef = 13u + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig1ToFreqmeasRef = 14u + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToFreqmeasRef = 15u + (FREQMEAS_REF_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig1ToFreqmeasRef = 16u + (FREQMEAS_REF_REG << PMUX_SHIFT),

    /*!< Selection for frequency measurement target clock. */
    kINPUTMUX_ClkInToFreqmeasTar           = 1U + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_FroOsc12MToFreqmeasTar       = 2u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_FroHfDivToFreqmeasTar        = 3u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_Clk16K1ToFreqmeasTar         = 5u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_SlowClkToFreqmeasTar         = 6u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_FreqmeClkIn0ToFreqmeasTar    = 7u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_FreqmeClkIn1ToFreqmeasTar    = 8u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToFreqmeasTar        = 9u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToFreqmeasTar        = 10u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToFreqmeasTar = 11u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig1ToFreqmeasTar = 12u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToFreqmeasTar = 13u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig1ToFreqmeasTar = 14u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToFreqmeasTar = 15u + (FREQMEAS_TAR_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig1ToFreqmeasTar = 16u + (FREQMEAS_TAR_REG << PMUX_SHIFT),

    /*!< Cmp0 Trigger. */
    kINPUTMUX_ArmTxevToCmp0Trigger            = 1U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToCmp0Trigger           = 2U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToCmp0Trigger           = 3U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToCmp0Trigger           = 4U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToCmp0Trigger           = 5U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToCmp0Trigger            = 6U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M0ToCmp0Trigger          = 8U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToCmp0Trigger          = 9U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M0ToCmp0Trigger          = 10U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToCmp0Trigger          = 11U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M0ToCmp0Trigger          = 12U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToCmp0Trigger          = 13U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Lptmr0ToCmp0Trigger             = 14U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToCmp0Trigger      = 16U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToCmp0Trigger    = 17U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig1ToCmp0Trigger    = 18U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToCmp0Trigger    = 19U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig1ToCmp0Trigger    = 20U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToCmp0Trigger    = 21U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig1ToCmp0Trigger    = 22U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToCmp0Trigger = 25U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToCmp0Trigger = 26U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToCmp0Trigger = 27U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToCmp0Trigger = 28U + (CMP0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_WuuToCmp0Trigger                = 30U + (CMP0_TRIG_REG << PMUX_SHIFT),

    /*!< Cmp1 Trigger. */
    kINPUTMUX_ArmTxevToCmp1Trigger            = 1U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToCmp1Trigger           = 2U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToCmp1Trigger           = 3U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToCmp1Trigger           = 4U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToCmp1Trigger           = 5U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToCmp1Trigger            = 6U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M0ToCmp1Trigger          = 8U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToCmp1Trigger          = 9U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M0ToCmp1Trigger          = 10U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToCmp1Trigger          = 11U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M0ToCmp1Trigger          = 12U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToCmp1Trigger          = 13U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Lptmr0ToCmp1Trigger             = 14U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToCmp1Trigger      = 16U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToCmp1Trigger    = 17U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig1ToCmp1Trigger    = 18U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToCmp1Trigger    = 19U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig1ToCmp1Trigger    = 20U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToCmp1Trigger    = 21U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig1ToCmp1Trigger    = 22U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToCmp1Trigger = 25U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToCmp1Trigger = 26U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToCmp1Trigger = 27U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToCmp1Trigger = 28U + (CMP1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_WuuToCmp1Trigger                = 30U + (CMP1_TRIG_REG << PMUX_SHIFT),

    /*!< Adc0 Trigger. */
    kINPUTMUX_ArmTxevToAdc0Trigger            = 1U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToAdc0Trigger           = 2U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToAdc0Trigger           = 3U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToAdc0Trigger           = 4U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToAdc0Trigger           = 5U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToAdc0Trigger            = 6U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToAdc0Trigger            = 7U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M0ToAdc0Trigger          = 9U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M1ToAdc0Trigger          = 10U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M0ToAdc0Trigger          = 11U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M1ToAdc0Trigger          = 12U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M0ToAdc0Trigger          = 13U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M1ToAdc0Trigger          = 14U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Lptmr0ToAdc0Trigger             = 15U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToAdc0Trigger      = 17U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToAdc0Trigger    = 18U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig1ToAdc0Trigger    = 19U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToAdc0Trigger    = 20U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig1ToAdc0Trigger    = 21U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToAdc0Trigger    = 22U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig1ToAdc0Trigger    = 23U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToAdc0Trigger = 26U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToAdc0Trigger = 27U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToAdc0Trigger = 28U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToAdc0Trigger = 29U + (ADC0_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_WuuToAdc0Trigger                = 31U + (ADC0_TRIG0_REG << PMUX_SHIFT),

    /*!< Qdc0 Trigger. */
    kINPUTMUX_ArmTxevToQdc0Trigger            = 1U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToQdc0Trigger           = 2U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToQdc0Trigger           = 3U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToQdc0Trigger           = 4U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToQdc0Trigger           = 5U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToQdc0Trigger            = 6U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToQdc0Trigger            = 7U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToQdc0Trigger          = 9U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToQdc0Trigger          = 10U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToQdc0Trigger          = 11U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToQdc0Trigger          = 12U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToQdc0Trigger          = 13U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToQdc0Trigger          = 14U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToQdc0Trigger      = 15U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Trigger    = 16U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Trigger    = 17U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Trigger    = 18U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Trigger    = 19U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Trigger    = 20U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Trigger    = 21U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToQdc0Trigger            = 24U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToQdc0Trigger            = 25U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToQdc0Trigger            = 26U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToQdc0Trigger            = 27U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToQdc0Trigger            = 28U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToQdc0Trigger            = 29U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToQdc0Trigger            = 30U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToQdc0Trigger            = 31U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToQdc0Trigger            = 32U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToQdc0Trigger            = 33U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToQdc0Trigger           = 34U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToQdc0Trigger           = 35U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToQdc0Trigger = 36U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToQdc0Trigger = 37U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToQdc0Trigger = 38U + (QDC0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToQdc0Trigger = 39U + (QDC0_TRIG_REG << PMUX_SHIFT),

    /*!< Qdc0 Home. */
    kINPUTMUX_ArmTxevToQdc0Home            = 1U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToQdc0Home           = 2U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToQdc0Home           = 3U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToQdc0Home           = 4U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToQdc0Home           = 5U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToQdc0Home            = 6U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToQdc0Home            = 7U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToQdc0Home          = 9U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToQdc0Home          = 10U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToQdc0Home          = 11U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToQdc0Home          = 12U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToQdc0Home          = 13U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToQdc0Home          = 14U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToQdc0Home      = 15U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Home    = 16U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Home    = 17U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Home    = 18U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Home    = 19U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Home    = 20U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Home    = 21U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToQdc0Home            = 24U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToQdc0Home            = 25U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToQdc0Home            = 26U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToQdc0Home            = 27U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToQdc0Home            = 28U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToQdc0Home            = 29U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToQdc0Home            = 30U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToQdc0Home            = 31U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToQdc0Home            = 32U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToQdc0Home            = 33U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToQdc0Home           = 34U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToQdc0Home           = 35U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToQdc0Home = 36U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToQdc0Home = 37U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToQdc0Home = 38U + (QDC0_HOME_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToQdc0Home = 39U + (QDC0_HOME_REG << PMUX_SHIFT),

    /*!< Qdc0 Index. */
    kINPUTMUX_ArmTxevToQdc0Index            = 1U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToQdc0Index           = 2U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToQdc0Index           = 3U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToQdc0Index           = 4U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToQdc0Index           = 5U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToQdc0Index            = 6U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToQdc0Index            = 7U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToQdc0Index          = 9U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToQdc0Index          = 10U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToQdc0Index          = 11U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToQdc0Index          = 12U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToQdc0Index          = 13U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToQdc0Index          = 14U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToQdc0Index      = 15U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Index    = 16U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Index    = 17U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Index    = 18U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Index    = 19U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Index    = 20U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Index    = 21U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToQdc0Index            = 24U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToQdc0Index            = 25U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToQdc0Index            = 26U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToQdc0Index            = 27U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToQdc0Index            = 28U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToQdc0Index            = 29U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToQdc0Index            = 30U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToQdc0Index            = 31U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToQdc0Index            = 32U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToQdc0Index            = 33U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToQdc0Index           = 34U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToQdc0Index           = 35U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToQdc0Index = 36U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToQdc0Index = 37U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToQdc0Index = 38U + (QDC0_INDEX_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToQdc0Index = 39U + (QDC0_INDEX_REG << PMUX_SHIFT),

    /*!< Qdc0 Phaseb. */
    kINPUTMUX_ArmTxevToQdc0Phaseb            = 1U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToQdc0Phaseb           = 2U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToQdc0Phaseb           = 3U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToQdc0Phaseb           = 4U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToQdc0Phaseb           = 5U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToQdc0Phaseb            = 6U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToQdc0Phaseb            = 7U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToQdc0Phaseb          = 9U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToQdc0Phaseb          = 10U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToQdc0Phaseb          = 11U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToQdc0Phaseb          = 12U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToQdc0Phaseb          = 13U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToQdc0Phaseb          = 14U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToQdc0Phaseb      = 15U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Phaseb    = 16U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Phaseb    = 17U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Phaseb    = 18U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Phaseb    = 19U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Phaseb    = 20U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Phaseb    = 21U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToQdc0Phaseb            = 24U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToQdc0Phaseb            = 25U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToQdc0Phaseb            = 26U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToQdc0Phaseb            = 27U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToQdc0Phaseb            = 28U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToQdc0Phaseb            = 29U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToQdc0Phaseb            = 30U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToQdc0Phaseb            = 31U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToQdc0Phaseb            = 32U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToQdc0Phaseb            = 33U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToQdc0Phaseb           = 34U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToQdc0Phaseb           = 35U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToQdc0Phaseb = 36U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToQdc0Phaseb = 37U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToQdc0Phaseb = 38U + (QDC0_PHASEB_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToQdc0Phaseb = 39U + (QDC0_PHASEB_REG << PMUX_SHIFT),

    /*!< Qdc0 Phasea. */
    kINPUTMUX_ArmTxevToQdc0Phasea            = 1U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToQdc0Phasea           = 2U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToQdc0Phasea           = 3U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToQdc0Phasea           = 4U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToQdc0Phasea           = 5U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToQdc0Phasea            = 6U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToQdc0Phasea            = 7U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToQdc0Phasea          = 9U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToQdc0Phasea          = 10U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToQdc0Phasea          = 11U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToQdc0Phasea          = 12U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToQdc0Phasea          = 13U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToQdc0Phasea          = 14U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToQdc0Phasea      = 15U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Phasea    = 16U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Phasea    = 17U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Phasea    = 18U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Phasea    = 19U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Phasea    = 20U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Phasea    = 21U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToQdc0Phasea            = 24U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToQdc0Phasea            = 25U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToQdc0Phasea            = 26U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToQdc0Phasea            = 27U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToQdc0Phasea            = 28U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToQdc0Phasea            = 29U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToQdc0Phasea            = 30U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToQdc0Phasea            = 31U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToQdc0Phasea            = 32U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToQdc0Phasea            = 33U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToQdc0Phasea           = 34U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToQdc0Phasea           = 35U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToQdc0Phasea = 36U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToQdc0Phasea = 37U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToQdc0Phasea = 38U + (QDC0_PHASEA_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToQdc0Phasea = 39U + (QDC0_PHASEA_REG << PMUX_SHIFT),

    /*!< Qdc0 Icap1. */
    kINPUTMUX_ArmTxevToQdc0Icap1            = 1U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToQdc0Icap1           = 2U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToQdc0Icap1           = 3U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToQdc0Icap1           = 4U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToQdc0Icap1           = 5U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToQdc0Icap1            = 6U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToQdc0Icap1            = 7U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToQdc0Icap1          = 9U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToQdc0Icap1          = 10U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToQdc0Icap1          = 11U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToQdc0Icap1          = 12U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToQdc0Icap1          = 13U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToQdc0Icap1          = 14U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToQdc0Icap1      = 15U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Icap1    = 16U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Icap1    = 17U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Icap1    = 18U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Icap1    = 19U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Icap1    = 20U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Icap1    = 21U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToQdc0Icap1            = 24U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToQdc0Icap1            = 25U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToQdc0Icap1            = 26U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToQdc0Icap1            = 27U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToQdc0Icap1            = 28U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToQdc0Icap1            = 29U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToQdc0Icap1            = 30U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToQdc0Icap1            = 31U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToQdc0Icap1            = 32U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToQdc0Icap1            = 33U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToQdc0Icap1           = 34U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToQdc0Icap1           = 35U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToQdc0Icap1 = 36U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToQdc0Icap1 = 37U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToQdc0Icap1 = 38U + (QDC0_ICAP1_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToQdc0Icap1 = 39U + (QDC0_ICAP1_REG << PMUX_SHIFT),

    /*!< FlexPWM0_SM0_EXTA0 input trigger connections. */
    kINPUTMUX_ArmTxevToFlexPwm0Sm0Exta0            = 1U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm0Exta0           = 2U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm0Exta0           = 3U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm0Exta0           = 4U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm0Exta0           = 5U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToFlexPwm0Sm0Exta0            = 6U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToFlexPwm0Sm0Exta0            = 7U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm0Exta0          = 9U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Exta0          = 10U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm0Exta0          = 11U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Exta0          = 12U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm0Exta0          = 13U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Exta0          = 14U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm0Exta0       = 15U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm0Exta0       = 16U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm0Exta0       = 17U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm0Exta0       = 18U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm0Exta0      = 19U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToFlexPwm0Sm0Exta0            = 20U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToFlexPwm0Sm0Exta0            = 21U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToFlexPwm0Sm0Exta0            = 22U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToFlexPwm0Sm0Exta0            = 23U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToFlexPwm0Sm0Exta0            = 24U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToFlexPwm0Sm0Exta0            = 25U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToFlexPwm0Sm0Exta0            = 26U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToFlexPwm0Sm0Exta0            = 27U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToFlexPwm0Sm0Exta0            = 28U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToFlexPwm0Sm0Exta0            = 29U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToFlexPwm0Sm0Exta0           = 30U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToFlexPwm0Sm0Exta0           = 31U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm0Exta0 = 32U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm0Exta0 = 33U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Exta0 = 34U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Exta0 = 35U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT),

    /*!< FlexPWM0_SM1_EXTA1 input trigger connections. */
    kINPUTMUX_ArmTxevToFlexPwm0Sm1Exta1            = 1U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm1Exta1           = 2U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm1Exta1           = 3U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm1Exta1           = 4U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm1Exta1           = 5U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToFlexPwm0Sm1Exta1            = 6U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToFlexPwm0Sm1Exta1            = 7U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm1Exta1          = 9U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Exta1          = 10U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm1Exta1          = 11U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Exta1          = 12U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm1Exta1          = 13U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Exta1          = 14U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm1Exta1       = 15U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm1Exta1       = 16U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm1Exta1       = 17U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm1Exta1       = 18U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm1Exta1      = 19U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToFlexPwm0Sm1Exta1            = 20U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToFlexPwm0Sm1Exta1            = 21U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToFlexPwm0Sm1Exta1            = 22U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToFlexPwm0Sm1Exta1            = 23U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToFlexPwm0Sm1Exta1            = 24U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToFlexPwm0Sm1Exta1            = 25U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToFlexPwm0Sm1Exta1            = 26U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToFlexPwm0Sm1Exta1            = 27U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToFlexPwm0Sm1Exta1            = 28U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToFlexPwm0Sm1Exta1            = 29U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToFlexPwm0Sm1Exta1           = 30U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToFlexPwm0Sm1Exta1           = 31U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm1Exta1 = 32U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm1Exta1 = 33U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Exta1 = 34U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Exta1 = 35U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT),

    /*!< FlexPWM0_SM2_EXTA2 input trigger connections. */
    kINPUTMUX_ArmTxevToFlexPwm0Sm2Exta2            = 1U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm2Exta2           = 2U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm2Exta2           = 3U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm2Exta2           = 4U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm2Exta2           = 5U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToFlexPwm0Sm2Exta2            = 6U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToFlexPwm0Sm2Exta2            = 7U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm2Exta2          = 9U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Exta2          = 10U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm2Exta2          = 11U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Exta2          = 12U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm2Exta2          = 13U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Exta2          = 14U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm2Exta2       = 15U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm2Exta2       = 16U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm2Exta2       = 17U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm2Exta2       = 18U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm2Exta2      = 19U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToFlexPwm0Sm2Exta2            = 20U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToFlexPwm0Sm2Exta2            = 21U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToFlexPwm0Sm2Exta2            = 22U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToFlexPwm0Sm2Exta2            = 23U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToFlexPwm0Sm2Exta2            = 24U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToFlexPwm0Sm2Exta2            = 25U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToFlexPwm0Sm2Exta2            = 26U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToFlexPwm0Sm2Exta2            = 27U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToFlexPwm0Sm2Exta2            = 28U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToFlexPwm0Sm2Exta2            = 29U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToFlexPwm0Sm2Exta2           = 30U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToFlexPwm0Sm2Exta2           = 31U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm2Exta2 = 32U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm2Exta2 = 33U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Exta2 = 34U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Exta2 = 35U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT),

    /*!< FlexPWM0_SM0_EXTSYNC0 input trigger connections. */
    kINPUTMUX_ArmTxevToFlexPwm0Sm0Extsync0            = 1U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm0Extsync0           = 2U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm0Extsync0           = 3U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm0Extsync0           = 4U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm0Extsync0           = 5U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToFlexPwm0Sm0Extsync0            = 6U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToFlexPwm0Sm0Extsync0            = 7U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm0Extsync0          = 9U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Extsync0          = 10U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm0Extsync0          = 11U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Extsync0          = 12U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm0Extsync0          = 13U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Extsync0          = 14U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm0Extsync0       = 15U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm0Extsync0       = 16U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm0Extsync0       = 17U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm0Extsync0       = 18U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm0Extsync0      = 19U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToFlexPwm0Sm0Extsync0            = 20U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToFlexPwm0Sm0Extsync0            = 21U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToFlexPwm0Sm0Extsync0            = 22U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToFlexPwm0Sm0Extsync0            = 23U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToFlexPwm0Sm0Extsync0            = 24U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToFlexPwm0Sm0Extsync0            = 25U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToFlexPwm0Sm0Extsync0            = 26U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToFlexPwm0Sm0Extsync0            = 27U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToFlexPwm0Sm0Extsync0            = 28U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToFlexPwm0Sm0Extsync0            = 29U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToFlexPwm0Sm0Extsync0           = 30U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToFlexPwm0Sm0Extsync0           = 31U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm0Extsync0 = 32U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm0Extsync0 = 33U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Extsync0 = 34U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Extsync0 = 35U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT),

    /*!< FlexPWM0_SM1_EXTSYNC1 input trigger connections. */
    kINPUTMUX_ArmTxevToFlexPwm0Sm1Extsync1            = 1U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm1Extsync1           = 2U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm1Extsync1           = 3U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm1Extsync1           = 4U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm1Extsync1           = 5U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToFlexPwm0Sm1Extsync1            = 6U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToFlexPwm0Sm1Extsync1            = 7U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm1Extsync1          = 9U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Extsync1          = 10U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm1Extsync1          = 11U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Extsync1          = 12U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm1Extsync1          = 13U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Extsync1          = 14U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm1Extsync1       = 15U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm1Extsync1       = 16U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm1Extsync1       = 17U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm1Extsync1       = 18U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm1Extsync1      = 19U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToFlexPwm0Sm1Extsync1            = 20U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToFlexPwm0Sm1Extsync1            = 21U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToFlexPwm0Sm1Extsync1            = 22U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToFlexPwm0Sm1Extsync1            = 23U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToFlexPwm0Sm1Extsync1            = 24U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToFlexPwm0Sm1Extsync1            = 25U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToFlexPwm0Sm1Extsync1            = 26U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToFlexPwm0Sm1Extsync1            = 27U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToFlexPwm0Sm1Extsync1            = 28U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToFlexPwm0Sm1Extsync1            = 29U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToFlexPwm0Sm1Extsync1           = 30U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToFlexPwm0Sm1Extsync1           = 31U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm1Extsync1 = 32U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm1Extsync1 = 33U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Extsync1 = 34U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Extsync1 = 35U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT),

    /*!< FlexPWM0_SM2_EXTSYNC2 input trigger connections. */
    kINPUTMUX_ArmTxevToFlexPwm0Sm2Extsync2            = 1U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToFlexPwm0Sm2Extsync2           = 2U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToFlexPwm0Sm2Extsync2           = 3U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToFlexPwm0Sm2Extsync2           = 4U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToFlexPwm0Sm2Extsync2           = 5U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToFlexPwm0Sm2Extsync2            = 6U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToFlexPwm0Sm2Extsync2            = 7U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToFlexPwm0Sm2Extsync2          = 9U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Extsync2          = 10U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToFlexPwm0Sm2Extsync2          = 11U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Extsync2          = 12U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToFlexPwm0Sm2Extsync2          = 13U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Extsync2          = 14U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm2Extsync2       = 15U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm2Extsync2       = 16U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm2Extsync2       = 17U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm2Extsync2       = 18U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm2Extsync2      = 19U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToFlexPwm0Sm2Extsync2            = 20U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToFlexPwm0Sm2Extsync2            = 21U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToFlexPwm0Sm2Extsync2            = 22U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToFlexPwm0Sm2Extsync2            = 23U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToFlexPwm0Sm2Extsync2            = 24U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToFlexPwm0Sm2Extsync2            = 25U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToFlexPwm0Sm2Extsync2            = 26U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToFlexPwm0Sm2Extsync2            = 27U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToFlexPwm0Sm2Extsync2            = 28U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToFlexPwm0Sm2Extsync2            = 29U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToFlexPwm0Sm2Extsync2           = 30U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToFlexPwm0Sm2Extsync2           = 31U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm2Extsync2 = 32U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm2Extsync2 = 33U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Extsync2 = 34U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Extsync2 = 35U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT),

    /*!< FlexPWM0_FAULT input trigger connections. */
    kINPUTMUX_ArmTxevToFlexPwm0Fault            = 1U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToFlexPwm0Fault           = 2U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToFlexPwm0Fault           = 3U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToFlexPwm0Fault           = 4U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToFlexPwm0Fault           = 5U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToFlexPwm0Fault            = 6U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToFlexPwm0Fault            = 7U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToFlexPwm0Fault          = 9U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToFlexPwm0Fault          = 10U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToFlexPwm0Fault          = 11U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToFlexPwm0Fault          = 12U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToFlexPwm0Fault          = 13U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToFlexPwm0Fault          = 14U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Fault       = 15U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Fault       = 16U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Fault       = 17U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Fault       = 18U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Fault      = 19U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToFlexPwm0Fault            = 20U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToFlexPwm0Fault            = 21U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToFlexPwm0Fault            = 22U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToFlexPwm0Fault            = 23U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToFlexPwm0Fault            = 24U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToFlexPwm0Fault            = 25U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToFlexPwm0Fault            = 26U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToFlexPwm0Fault            = 27U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToFlexPwm0Fault            = 28U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToFlexPwm0Fault            = 29U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToFlexPwm0Fault           = 30U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToFlexPwm0Fault           = 31U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Fault = 32U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Fault = 33U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault = 34U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault = 35U + (FlexPWM0_FAULT_REG << PMUX_SHIFT),

    /*!< FlexPWM0_FORCE input trigger connections. */
    kINPUTMUX_ArmTxevToFlexPwm0Force            = 1U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToFlexPwm0Force           = 2U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToFlexPwm0Force           = 3U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToFlexPwm0Force           = 4U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToFlexPwm0Force           = 5U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToFlexPwm0Force            = 6U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToFlexPwm0Force            = 7U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToFlexPwm0Force          = 9U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToFlexPwm0Force          = 10U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToFlexPwm0Force          = 11U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToFlexPwm0Force          = 12U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToFlexPwm0Force          = 13U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToFlexPwm0Force          = 14U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Force       = 15U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Force       = 16U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Force       = 17U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Force       = 18U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Force      = 19U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToFlexPwm0Force            = 20U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToFlexPwm0Force            = 21U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToFlexPwm0Force            = 22U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToFlexPwm0Force            = 23U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToFlexPwm0Force            = 24U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToFlexPwm0Force            = 25U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToFlexPwm0Force            = 26U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToFlexPwm0Force            = 27U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToFlexPwm0Force            = 28U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToFlexPwm0Force            = 29U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToFlexPwm0Force           = 30U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToFlexPwm0Force           = 31U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Force = 32U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Force = 33U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Force = 34U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Force = 35U + (FlexPWM0_FORCE_REG << PMUX_SHIFT),

    /*!< PWM0 external clock trigger. */
    kINPUTMUX_Clk16K1ToPwm0ExtClk    = 1U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),
    kINPUTMUX_ClkInToPwm0ExtClk      = 2U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToPwm0ExtClk   = 3U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToPwm0ExtClk   = 4U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),
    kINPUTMUX_ExttrigIn0ToPwm0ExtClk = 5U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),
    kINPUTMUX_ExttrigIn7ToPwm0ExtClk = 6U + (PWM0_EXT_CLK_REG << PMUX_SHIFT),

    /*!< AOI0 trigger input connections. */
    kINPUTMUX_Adc0Tcomp0ToAoi0Mux         = 1U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp1ToAoi0Mux         = 2U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp2ToAoi0Mux         = 3U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Adc0Tcomp3ToAoi0Mux         = 4U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToAoi0Mux            = 5U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToAoi0Mux            = 6U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M0ToAoi0Mux          = 8U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M1ToAoi0Mux          = 9U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToAoi0Mux          = 10U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToAoi0Mux          = 11U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M0ToAoi0Mux          = 12U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M1ToAoi0Mux          = 13U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToAoi0Mux          = 14U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToAoi0Mux          = 15U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M0ToAoi0Mux          = 16U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M1ToAoi0Mux          = 17U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToAoi0Mux          = 18U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToAoi0Mux          = 19U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Lptmr0ToAoi0Mux             = 20U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag0ToAoi0Mux       = 22U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag1ToAoi0Mux       = 23U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag2ToAoi0Mux       = 24U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0CmpFlag3ToAoi0Mux       = 25U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Qdc0PosMatchToAoi0Mux       = 26U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig0ToAoi0Mux    = 27U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm0OutTrig1ToAoi0Mux    = 28U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig0ToAoi0Mux    = 29U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm1OutTrig1ToAoi0Mux    = 30U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig0ToAoi0Mux    = 31U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Pwm0Sm2OutTrig1ToAoi0Mux    = 32U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToAoi0Mux            = 35U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToAoi0Mux            = 36U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToAoi0Mux            = 37U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToAoi0Mux            = 38U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToAoi0Mux            = 39U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToAoi0Mux            = 40U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToAoi0Mux            = 41U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToAoi0Mux            = 42U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToAoi0Mux            = 43U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToAoi0Mux            = 44U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToAoi0Mux           = 45U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToAoi0Mux           = 46U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToAoi0Mux = 47U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToAoi0Mux = 48U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToAoi0Mux = 49U + (AOI0_MUX_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToAoi0Mux = 50U + (AOI0_MUX_REG << PMUX_SHIFT),

    /*!< USB-FS trigger input connections. */
    kINPUTMUX_Lpuart0TrgTxdataToUsbfsTrigger = 1U + (USBFS_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Lpuart1TrgTxdataToUsbfsTrigger = 2U + (USBFS_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Lpuart2TrgTxdataToUsbfsTrigger = 3U + (USBFS_TRIG_REG << PMUX_SHIFT),

    /*!< EXT trigger connections. */
    kINPUTMUX_ArmTxevToExtTrigger  = 1U + (EXT_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToExtTrigger = 2U + (EXT_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToExtTrigger = 3U + (EXT_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToExtTrigger = 4U + (EXT_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToExtTrigger = 5U + (EXT_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToExtTrigger  = 6U + (EXT_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToExtTrigger  = 7U + (EXT_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Lpuart0ToExtTrigger  = 9U + (EXT_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Lpuart1ToExtTrigger  = 10U + (EXT_TRIG0_REG << PMUX_SHIFT),
    kINPUTMUX_Lpuart2ToExtTrigger  = 11U + (EXT_TRIG0_REG << PMUX_SHIFT),

    /*!< LPI2C0 trigger input connections. */
    kINPUTMUX_ArmTxevToLpi2c0Trigger            = 1U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToLpi2c0Trigger           = 2U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToLpi2c0Trigger           = 3U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToLpi2c0Trigger           = 4U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToLpi2c0Trigger           = 5U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToLpi2c0Trigger            = 6U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToLpi2c0Trigger            = 7U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M0ToLpi2c0Trigger          = 9U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M1ToLpi2c0Trigger          = 10U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M0ToLpi2c0Trigger          = 11U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M1ToLpi2c0Trigger          = 12U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M0ToLpi2c0Trigger          = 13U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M1ToLpi2c0Trigger          = 14U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Lptmr0ToLpi2c0Trigger             = 15U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToLpi2c0Trigger            = 17U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToLpi2c0Trigger            = 18U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToLpi2c0Trigger            = 19U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToLpi2c0Trigger            = 20U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToLpi2c0Trigger            = 21U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToLpi2c0Trigger            = 22U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToLpi2c0Trigger            = 23U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToLpi2c0Trigger            = 24U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToLpi2c0Trigger = 25U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToLpi2c0Trigger = 26U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToLpi2c0Trigger = 27U + (LPI2C0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToLpi2c0Trigger = 28U + (LPI2C0_TRIG_REG << PMUX_SHIFT),

    /*!< LPSPI0 trigger input connections. */
    kINPUTMUX_ArmTxevToLpspi0Trigger            = 1U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToLpspi0Trigger           = 2U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToLpspi0Trigger           = 3U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToLpspi0Trigger           = 4U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToLpspi0Trigger           = 5U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToLpspi0Trigger            = 6U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToLpspi0Trigger            = 7U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M0ToLpspi0Trigger          = 9U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M1ToLpspi0Trigger          = 10U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M0ToLpspi0Trigger          = 11U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M1ToLpspi0Trigger          = 12U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M0ToLpspi0Trigger          = 13U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M1ToLpspi0Trigger          = 14U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Lptmr0ToLpspi0Trigger             = 15U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToLpspi0Trigger            = 17U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToLpspi0Trigger            = 18U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToLpspi0Trigger            = 19U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToLpspi0Trigger            = 20U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToLpspi0Trigger            = 21U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToLpspi0Trigger            = 22U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToLpspi0Trigger            = 23U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToLpspi0Trigger            = 24U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToLpspi0Trigger = 25U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToLpspi0Trigger = 26U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToLpspi0Trigger = 27U + (LPSPI0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToLpspi0Trigger = 28U + (LPSPI0_TRIG_REG << PMUX_SHIFT),

    /*!< LPSPI1 trigger input connections. */
    kINPUTMUX_ArmTxevToLpspi1Trigger            = 1U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToLpspi1Trigger           = 2U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToLpspi1Trigger           = 3U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToLpspi1Trigger           = 4U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToLpspi1Trigger           = 5U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToLpspi1Trigger            = 6U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToLpspi1Trigger            = 7U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M0ToLpspi1Trigger          = 9U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M1ToLpspi1Trigger          = 10U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M0ToLpspi1Trigger          = 11U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M1ToLpspi1Trigger          = 12U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M0ToLpspi1Trigger          = 13U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M1ToLpspi1Trigger          = 14U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Lptmr0ToLpspi1Trigger             = 15U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToLpspi1Trigger            = 17U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToLpspi1Trigger            = 18U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToLpspi1Trigger            = 19U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToLpspi1Trigger            = 20U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToLpspi1Trigger            = 21U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToLpspi1Trigger            = 22U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToLpspi1Trigger            = 23U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToLpspi1Trigger            = 24U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToLpspi1Trigger = 25U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToLpspi1Trigger = 26U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToLpspi1Trigger = 27U + (LPSPI1_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToLpspi1Trigger = 28U + (LPSPI1_TRIG_REG << PMUX_SHIFT),

    /*!< LPUART0 trigger input connections. */
    kINPUTMUX_ArmTxevToLpuart0Trigger                 = 1U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out0ToLpuart0Trigger                = 2U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out1ToLpuart0Trigger                = 3U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out2ToLpuart0Trigger                = 4U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Aoi0Out3ToLpuart0Trigger                = 5U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp0OutToLpuart0Trigger                 = 6U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Cmp1OutToLpuart0Trigger                 = 7U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M2ToLpuart0Trigger               = 9U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer0M3ToLpuart0Trigger               = 10U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M2ToLpuart0Trigger               = 11U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer1M3ToLpuart0Trigger               = 12U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M2ToLpuart0Trigger               = 13U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Ctimer2M3ToLpuart0Trigger               = 14U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Lptmr0ToLpuart0Trigger                  = 15U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn0ToLpuart0Trigger                 = 17U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn1ToLpuart0Trigger                 = 18U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn2ToLpuart0Trigger                 = 19U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn3ToLpuart0Trigger                 = 20U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn4ToLpuart0Trigger                 = 21U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn5ToLpuart0Trigger                 = 22U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn6ToLpuart0Trigger                 = 23U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn7ToLpuart0Trigger                 = 24U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn8ToLpuart0Trigger                 = 25U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn9ToLpuart0Trigger                 = 26U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn10ToLpuart0Trigger                = 27U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_TrigIn11ToLpuart0Trigger                = 28U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio0PinEventTrig0ToLpuart0Trigger      = 29U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio1PinEventTrig0ToLpuart0Trigger      = 30U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio2PinEventTrig0ToLpuart0Trigger      = 31U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Gpio3PinEventTrig0ToLpuart0Trigger      = 32U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_WuuToLpuart0Trigger                     = 34U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart0Trigger = 35U + (LPUART0_TRIG_REG << PMUX_SHIFT),
} inputmux_connection_t;

/*@}*/

/*@}*/

#endif /* _FSL_INPUTMUX_CONNECTIONS_ */
